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order this document by MPC823ele/d revision 1 MPC823 ac electrical specifications this document contains information on a product under development. motorola reserves the right to change or discontinue this p roduct without notice. powerpc is a registered trademark of ibm corp. and is used by motorola under license from ibm corp. i 2 c is a registered trademark of philips corporation. 2000 motorola, inc.all rights reserved. this document contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications for the MPC823. this device contains circuitry protecting against damage from high-static voltage or electrical fields. however, it is advised that precautions be taken to avoid application of any voltages higher than the maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either gnd or v cc ). note: visit our website at www.motorola.com if you are using a frequency other than 25, 40, or 50mhz. our website contains a spreadsheet that you can use to calculate the timing for your specific system frequency.
2 MPC823 electrical specifications motorola maximum ratings (gnd = 0v) thermal characteristics rating symbol value unit supply voltage vddh -0.3 to 4.0 v vdd -0.3 to 4.0 v kapwr -0.3 to 4.0 v vddsyn -0.3 to 4.0 v input voltage (jtag and gpio) vin -0.3 to 5.8 v input voltage (all other pins) vin -0.3 to 3.3 v operating temperature t a 0 to 70? or -40? to 85? ?c storage temperature range t stg -55 to +150 ?c notes: 1. functional operating conditions are given in dc electrical characteristics (vcc = 3.0 - 3.6 v) . absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : the jtag and gpio input voltages cannot be more than 2.5 v greater than supply voltage, this restriction applies also on power-on as well as on normal operation. 3. 5 volt friendly inputs are inputs that tolerate 5 volts for jtag and gpio pins. 4. if you are using mask revision base #f98s (revision 0), all pins except extal and clk4in are 5v tolerant inputs. characteristic symbol value unit thermal resistance for bga q jc ~30 c/w
motorola MPC823 electrical specifications 3 power considerations the average chip-junction temperature , t j , in c can be obtained from t j = t a + (p d q ja ) (1) where t a = ambient temperature , c q ja = package thermal resistance , junction to ambient , c/w p d =p int + p i/o p int =i dd x v dd , watts?chip internal power p i/o = power dissipation on input and output pins?user determined for most applications p i/o < 0.3 p int and can be neglected. if p i/o is neglected , an approximate relationship between p d and t j is: p d =k ? (t j + 273 c) (2) solving equations (1) and (2) for k gives k = p d (t a + 273 c) + q ja p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . layout practices each v cc pin on the MPC823 should be provided with a low-impedance path to the board?s supply. each gnd pin should be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 m f bypass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and gnd should be kept to less than half an inch per capacitor lead. a four-layer board that employs two inner layers as v cc and gnd planes should be used. all output pins on the MPC823 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data busses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins.
4 MPC823 electrical specifications motorola dc electrical characteristics (v cc = 3.0 - 3.6 v) characteristic symbol min max unit input high voltage (for jtag and gpio) v ih 2.0 5.5 v input high voltage (all other pins) v ih 2.0 3.6 v input low voltage v il gnd 0.8 v extal and extclk input high voltage v ihc 0.7*(v cc )v cc +0.3 v input leakage current, v in = 5.5 v i in ? 10 a hi-z (off state) leakage current, v in = 3.5v i oz ? 10 a signal low input current, v il = 0.8 v i l 10 a signal high input current, v ih = 2.0 v i h 10 a output high voltage, i oh = e2.0 ma , v ddh = 3.0v except xtal, xfc, and open-drain pins v oh 2.4 ? v output low voltage iol = 2.0 ma clkout iol = 3.2 maa[6:31], tsiz0/reg , tsiz1, d(0:31), dp[0:3]/irq [3:6], rd/wr , burst , rsv /irq2 , ip_b[0:1]/iwp[0:1]/vfls[0:1], ip_b2/ iois16_b /at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/ vf1, ip_b6/dsdi/at0, ip_b7/ptr /at3, usbrxd/pa15, rxd2/ pa13, smrxd2/l1txda/pa9, smtxd2/l1rxda/pa8, irq4 /kr / spkrout, tin1/l1rclka/brgo1/clk1/pa7, tin3/tout1 / clk2/pa6, tin2/l1tclka/brgo2/clk3/pa5, tin4/tout2 /clk4/ pa4, lcd_a/spisel /pb31, spiclk/pb30, spimosi/pb29, brgo3/spimiso/pb28, brgo1/i2csda/pb27, brgo2/i2cscl/ pb26, smtxd1/pb25, smrxd1/pb24, smsyn1 /sdack1 /pb23, smsyn2 /sdack2 /pb22, lcd_b/l1st1/pb19, l1st2/rts2 / pb18, lcd_c/l1st3/pb17, l1st4/l1rqa/pb16, l1st5/dreq1 / pc15, l1st6/rts2 /dreq2 /pc14, l1st7/pc13, l1st8/l1rqa/ pc12, usbrxp/pc11, usbrxn/tgate1 /pc10, cts2 /pc9, tgate1 /cd2 /pc8, usbtxp/pc7, usbtxn/pc6, sdack1 / l1tsynca/pc5, l1rsynca/pc4, ld8/vd7/pd15, ld7/vd6/ pd14, ld6/vd5/pd13, ld5/vd4/pd12, ld4/vd3/pd11, ld3/vd2/ pd10, ld2/vd1/pd9, ld1/vd0/pd8, frame/vsync/pd5, lcd_ac/loe/blank/pd6, ld0/field/pd7, load/hsync/pd4, shift/clk/pd3 v ol ? 0.5 v iol = 5.3 mabdip /gpl_b 5 , br , bg , frz/irq6 , cs [0:5], cs 6 / ce 1_b , cs 7 /ce 2_b , we0 /bs_ab0 /iord , we1 /bs_ab1 /iowr , we2 /bs_ab2 /pcoe , we3 /bs_ab3 /pcwe , gpl_a 0 /gpl_b 0 , oe / gpl_a 1 /gpl_b 1 , gpl_a [2:3]/gpl_b [2:3]/cs [2:3], upwaita/ gpl_a 4 /as , upwaitb/gpl_b 4 , gpl_a 5 , ale_b/dsck/at1, op2/modck1/sts , op3/modck2/dsdo iol = 7.0 ma usboe /pa14, txd2/pa12 iol = 8.9 mats , ta , tea , bi , bb , hreset , sreset note: input pin voltage specifications are v cc = +4 v or 5.8 v, whichever is less. ac timings are based on a 50 p | load. if you are using mask revision base #f98s, all pins except extal and clk4in are 5v tolerant inputs.
motorola MPC823 electrical specifications 5 ac electrical characteristics clkout outputs inputs inputs 2.0v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v outputs 2.0v 0.8v 0.8v 2.0v 0.8v c d a b c d a b a = maximum output delay specification b = minimum output hold time c = minimum input setup time specification d = minimum input hold time specification
6 MPC823 electrical specifications motorola external bus electrical characteristics table 1. bus operation timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max b1 clkout period 40 ? 25 ? 20 ? ns b1a extclk to clkout phase skew (extclk>15mhz and mf 2) -0.9 0.9 -0.9 0.9 -0.9 0.9 ns b1b extclk to clkout phase skew (extclk>10mhz and mf 10) -2.3 2.3 -2.3 2.3 -2.3 2.3 ns b1c clkout phase jitter (extclk>15mhz and mf 2) -0.6 0.6 -0.6 0.6 -0.6 0.6 ns b1d clkout phase jitter (extclk>10mhz and mf 10) -22-22-22ns b1e clkout frequency jitter (mf<10) ? 0.5 ? 0.5 ? 0.5 % b1f clkout frequency jitter (10500) ?3?3?3 % b1h frequency jitter on extclk ? 0.5 ? 0.5 ? 0.5 % b2 clock pulse width low 16 ? 10 ? 8 ? ns b3 clock pulse width high 16 ? 10 ? 8 ? ns b4 clkout rise time ?4?4?4 ns b5 clkout fall time ?4?4?4 ns b6 n/a (used on interactive spreadsheet) b7 clkout to a(6:31), rd/wr , burst , d(0:31), dp(0:3) invalid 10?5?5?ns b7a clkout to tsiz(0:1),reg , rsv , at(0:3),bdip , ptr invalid 10 ?5?5?ns b7b clkout to br , bg , frz, vfls(0:1), vf(0:2), iwp(0:2), lwp(0:1), sts invalid 10?5?5?ns b8 clkout to a(6:31), rd/wr , burst , d(0:31), dp(0:3) valid 10 19 5 13 5 12 ns b8a clkout to tsiz(0:1),reg , rsv , at(0:3), bdip , ptr valid 10 19 5 13 5 12 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 1019513512ns b9 clkout to a(6:31), rd/wr , burst , d(0:31), dp(0:3), tsiz(0:1),reg , rsv , at(0:3), ptr hi z 1019513512ns b10 n/a b11 clkout to ts , bb assertion 10 19 5 12.25 5 12.25 ns b11a clkout to ta , bi assertion (when driven by the memory controller or pcmcia interface) 2.5 11 2.5 9.25 2.5 9.25 ns b12 clkout to ts , bb negation 10 19 5 13 5 12 ns b12a clkout to ta , bi negation (when driven by the memory controller or pcmcia interface) 2.5 11 2.5 11 2.5 11 ns b13 clkout to ts , bb hi z 1024521519ns
motorola MPC823 electrical specifications 7 b13a clkout to ta , bi hi z (when driven by the memory controller or pcmcia interface) 2.5 15 2.5 15 2.5 16 ns b14 clkout to tea assertion 2.5 11 2.5 11 2.5 10 ns b15 clkout to tea hi z 2.5 15 2.5 15 2.5 15 ns b16 ta , bi valid to clkout (setup time) 9.75 ? 9.75 ? 9.75 ? ns b16a tea , kr , retry valid to clkout (setup time) 11 ? 10 ? 10 ? ns b16b bb , bg , br valid to clkout (setup time) 8.5 ? 8.5 ? 8.5 ? ns b17 clkout to ta , tea , bi , bb , bg , br valid (hold time) 1?1?1?ns b17a clkout to kr , retry valid (hold time) 2?2?2?ns b18 d(0:31), dp(0:3) valid to clkout rising edge (setup time) 6?6?6?ns b19 clkout rising edge to d(0:31), dp(0:3) valid (hold time) 2?2?2?ns b20 d(0:31), dp(0:3) valid to clkout falling edge (setup time) 4?4?4?ns b21 clkout falling edge to d(0:31), dp(0:3) valid (hold time) 2?2?2?ns b22 clkout rising edge to cs asserted -gpcm- acs = 00 10 20 5 13 5 13 ns b22a clkout falling edge to cs asserted -gpcm- acs = 10, trlx = 0 ?10?8?8 ns b22b clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 0 1020513513ns b22c clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 1 1425716716ns b23 clkout rising edge to cs negated -gpcm-read access - gpcm-write access, acs=00, trlx=0, csnt=0 3102828ns b24 a(6:31) to cs asserted -gpcm- acs = 10, trlx = 0 8?3?3?ns b24a a(6:31) to cs asserted -gpcm- acs = 11, trlx = 0 18 ?8?8?ns b25 clkout rising edge to oe , we (0:3) asserted ? 11 ?9?9 ns b26 clkout rising edge to oe negated 3 11 2929ns b27 a(6:31) to cs asserted -gpcm- acs = 10, trlx = 1 48 ? 23 ? 23 ? ns b27a a(6:31) to cs asserted -gpcm- acs = 11, trlx = 1 58 ? 28 ? 28 ? ns b28 clkout rising edge to we (0:3) negated -gpcm-write access csnt = ?0? ?11?9?9 ns b28a clkout falling edge to we (0:3) negated -gpcm-write access trlx = ?0?, csnt = ?1?, ebdf=0 1020513513ns b28b clkout falling edge to cs negated -gpcm-write access trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 ?20?13?13 ns table 1. bus operation timing (continued) num characteristic 25mhz 40mhz 50mhz unit min max min max min max
8 MPC823 electrical specifications motorola b28c clkout falling edge to we (0:3) negated -gpcm-write access trlx = ?0?, csnt = ?1?, ebdf=1 1425716716ns b28d clkout falling edge to cs negated -gpcm-write access trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 ?25?16?16 ns b29 we (0:3) negated to d(0:31), dp(0:3) hi z -gpcm- write access, csnt = ?0? 8?3?3?ns b29a we (0:3) negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 0 18?8?8?ns b29b cs negated to d(0:31), dp(0:3) hi z -gpcm- write access, acs = ?00?, trlx = ?0? & csnt = ?0? 8?3?3?ns b29c cs negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 18?8?8?ns b29d we (0:3) negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 0 58?28?28? ns b29e cs negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 58?28?28? ns b29f we (0:3) negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 1 12?5?5?ns b29g cs negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 12?5?5?ns b29h we (0:3) negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 1 52?24?24? ns b29i cs negated to d(0:31), dp(0:3) hi z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf =1 52?24?24? ns b30 cs , we (0:3) negated to a(6:31) invalid -gpcm- write access. 8?3?3? b30a we (0:3) negated to a(6:31) invalid -gpcm- write access, trlx=?0?, csnt = '1?. cs negated to a(6:31) invalid -gpcm- write access, trlx=?0?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 0 18?8?8?ns b30b we (0:3) negated to a(6:31)invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to a(6:31)invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 0 58?28?28? ns b30c we (0:3) negated to a(6:31) invalid -gpcm- write access, trlx=?0?, csnt = '1?. cs negated to a(6:31) invalid -gpcm- write access, trlx=?0?, csnt = '1?, acs = 10 ,acs = =?11?, ebdf = 1 12?4?4?ns b30d we (0:3) negated to a(6:31) invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to a(6:31) invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 52?24?24? ns b31 clkout falling edge to cs valid as requested by cst4 in the corresponding word of the upm 1.5 10 1.5 8 1.5 8 ns table 1. bus operation timing (continued) num characteristic 25mhz 40mhz 50mhz unit min max min max min max
motorola MPC823 electrical specifications 9 b31a clkout falling edge to cs valid as requested by cst1 in the corresponding word of the upm, ebdf = 0 1020513513ns b31b clkout rising edge to cs valid as requested by cst2 in the corresponding word of the upm 1.5 10 1.5 8 1.5 8 ns b31c clkout rising edge to cs valid as requested by cst3 in the corresponding word of the upm 1020513513ns b31d clkout falling edge to cs valid as requested by cst1 in the corresponding word of the upm, ebdf = 1 1025516516ns b32 clkout falling edge to bs valid as requested by bst4 in the corresponding word of the upm 1.5 10 1.5 8 1.5 8 ns b32a clkout falling edge to bs valid as requested by bst1 in the corresponding word of the upm, ebdf = 0 1020513513ns b32b clkout rising edge to bs valid as requested by bst2 in the corresponding word of the upm 1.5 10 1.5 8 1.5 8 ns b32c clkout rising edge to bs valid as requested by bst3 in the corresponding word of the upm 1020513513ns b32d clkout falling edge to bs valid as requested by bst1 in the corresponding word of the upm, ebdf = 1 1025516516ns b33 clkout falling edge to gpl valid as requested by gxt4 in the corresponding word of the upm 1.5 10 1.5 8 1.5 8 ns b33a clkout rising edge to gpl valid as requested by gxt3 in the corresponding word of the upm 1020513513ns b34 a(6:31) and d(0:31) to cs valid as requested by cst4 in the corresponding word of the upm 8?3?3?ns b34a a(6:31) and d(0:31) to cs valid as requested by cst1 in the corresponding word of the upm 18?8?8?ns b34b a(6:31) and d(0:31) to cs valid as requested by cst2 in the corresponding word of the upm 28?13?13? ns b35 a(6:31) and d(0:31) to bs valid as requested by bst4 in the corresponding word of the upm 8?3?3?ns b35a a(6:31) and d(0:31) to bs valid as requested by bst1 in the corresponding word of the upm 18?8?8?ns b35b a(6:31) and d(0:31) to bs valid as requested by bst2 in the corresponding word of the upm 28?13?13? ns b36 a(6:31) and d(0:31) to gpl valid as requested by gxt4 in the corresponding word of the upm 8?3?3?ns b37 upwait valid to clkout falling edge 6?6?6?ns b38 clkout falling edge to upwait valid 1?1?1?ns b39 as valid to clkout rising edge 9?7?7?ns table 1. bus operation timing (continued) num characteristic 25mhz 40mhz 50mhz unit min max min max min max
10 MPC823 electrical specifications motorola b40 a(6:31), tsiz(0:1), rd/wr , burst , valid to clkout rising edge 9?7?7?ns b41 ts valid to clkout rising edge (setup time) 9?7?7?ns b42 clkout rising edge to ts valid (hold time) 2?2?2?ns b43 as negation to memory controller signals negation ? 13 ? 13 ? 13 ns notes: 1. the timing for br output is relevant when the MPC823 is selected to work with the external bus arbiter. the timing for bg output is relevant when the MPC823 is selected to work with the internal bus arbiter. 2. the setup times required for t a , tea and bi are relevant only when they are supplied by an external device (and not when the memory controller or the pcmcia interface drive them). 3. the timing required for br input is relevant when the MPC823 is selected to work with the internal bus arbiter. the timing for bg input is relevant when the MPC823 is selected to work with the external bus arbiter. 4. the d(0:31) and dp(0:3) input timings b18 and b19 refer to the rising edge of the clkout in which the t a input signal is asserted. 5. the d(0:31) and dp(0:3) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only under control of the upm in the memory controller. 6. the timing b30 refers to cs when acs = ?00? and to we (0:3) when csnt = ?0?. 7. the signal upwait is considered asynchronous to the clkout and synchronized internally. the timings specited in b37 and b38 are specited to enable the freeze of the upm output signals. 8. the as signal is considered asynchronous to the clkout signal. figure 1. external clock timing diagram table 1. bus operation timing (continued) num characteristic 25mhz 40mhz 50mhz unit min max min max min max clkout b1 b1 b4 b5 b3 b2
motorola MPC823 electrical specifications 11 figure 2. synchronous output signals timing diagram clkout output signals output signals output signals b8 b9 b9 b8a b7a b7 b7b b8b
12 MPC823 electrical specifications motorola figure 3. synchronous active pull-up and open-drain outputs signals timing diagram clkout ts , bb tea ta , bi b11 b13 b13a b12 b12a b11a b14 b15
motorola MPC823 electrical specifications 13 figure 4. synchronous input signals timing diagram clkout ta , bi , tea tea , retry , kr bb , bg , br b16 b16a b16b b17 b17a b17
14 MPC823 electrical specifications motorola figure 5. input data in normal case timing diagram figure 6. input data when controlled by the upm timing diagram clkout ta d(0:31), dp(0:3) b16 b18 b19 b17 ta d(0:31), dp(0:3) clkout b20 b21
motorola MPC823 electrical specifications 15 figure 7. external bus read timing diagram (gpcm controlledeacs = ?00?) figure 8. external bus read timing diagram (gpcm controlledetrlx = ?0?, acs = ?10?) clkout b11 ts cs x oe we (0:3) d(0:31), dp(0:3) a(6:31) b8 b22a b28 b26 b18 b12 b23 b19 b25 clkout ts a(6:31) b11 cs x oe d(0:31), dp(0:3) b8 b12 b19 b25 b23 b22b b18 b24a b26 b22c
16 MPC823 electrical specifications motorola figure 9. external bus read timing diagram (gpcm controlledetrlx = ?0?, acs = ?11?) clkout ts a(6:31) b11 cs x oe d(0:31), dp(0:3) b12 b26 b19 b25 b23 b22b b18 b24a b22c b8
motorola MPC823 electrical specifications 17 figure 10. external bus read timing diagram (gpcm controlledetrlx = ?1?, acs = ?10?, acs = ?11?) clkout ts a(6:31) csx oe d(0:31), dp(0:3) b22a b18 b19 b27 b27a b22b b12 b26 b23 b11 b8 b22c
18 MPC823 electrical specifications motorola figure 11. external bus write timing diagram (gpcm controlledetrlx = ?0?, csnt = ?0?) clkout ts a(6:31) csx we (0:3) d(0:31), dp(0:3) b8 oe b12 b8 b11 b22 b28 b30 b23 b29b b26 b29 b9 b25
motorola MPC823 electrical specifications 19 figure 12. external bus write timing diagram (gpcm controlledetrlx = ?0?, csnt = ?1?) clkout ts a(6:31) cs x we (0:3) d(0:31), dp(0:3) oe b22 b11 b12 b30 b28c b9 b30a b28d b25 b8 b23 b28b b29g b29c b29f b29a b28a b8 b26
20 MPC823 electrical specifications motorola figure 13. external bus write timing diagram (gpcm controlledetrlx = ?1?, csnt = ?1?) clkout ts a(6:31) csx we (0:3) d(0:31), dp(0:3) oe b22 b11 b8 b12 b30d b30b b23 b28d b29e b29h b29d b29b b28c b28a b9 b8 b26 b25 b28b b29f
motorola MPC823 electrical specifications 21 figure 14. external bus timing diagram (upm-controlled signals) clkout a(6:31) gpla (0:5), gplb (0:5) cs x bs_ab (0:3) b8 b31 b31d b31a b31b b31c b32c b32b b33a b36 b33 b35b b35a b35 b32 b32a b32d b34b b34a b34
22 MPC823 electrical specifications motorola figure 15. asynchronous upwait asserted detection in upm handled cycles timing diagram clkout upwait cs x bs_ab (0:3) gpla (0:5), gplb (0:5) b37 b38
motorola MPC823 electrical specifications 23 figure 16. asynchronous upwait negated detection in upm handled cycles timing diagram figure 17. synchronous external master access timing diagram (gpcm handledeacs = ?00?) clkout upwait cs x bs_ab (0:3) gpla (0:5), gplb (0:5) b37 b38 clkout ts a(6:31), tsiz(0:1), cs x rd/wr , burst b40 b41 b42 b22
24 MPC823 electrical specifications motorola figure 18. asynchronous external master memory access timing diagram (gpcm controlledeacs = ?00?) figure 19. asynchronous external master timing diagram (control signals negation time) clkout as a(6:31), cs x tsiz(0:1), rd/wr b40 b39 b22 as cs x , we (0:3), oe , gpl x , bs (0:3), b43
motorola MPC823 electrical specifications 25 table 2. interrupt timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max i39 ir qx valid to clkout rising edge (setup time) 6 ? 6/6 ? 6/6 ? ns i40 irq x hold time after clkout 2 ? 2/2 ? 2/2 ? ns i41 irq x pulse width low 3 ? 3/3 ? 3/3 ? ns i42 irq x pulse width high 3 ? 3/3 ? 3/3 ? ns i43 irq x edge to edge time 160 ? 80/80 ? 80/80 ? ns notes: 1. the timings i39 and i40 describe the testing conditions under which the irq lines are tested when defined as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. 2. the timings i41 and i42 are specited to allow the correct function of the irq lines detection circuitry, and has no direct relation with the total system interrupt latency that the MPC823 can support. figure 20. interrupt detection timing diagram for external level-sensitive lines clkout irq x i39 i40
26 MPC823 electrical specifications motorola figure 21. interrupt detection timing diagram for external edge-sensitive lines clkout irq x i39 i43 i42 i41 i43
motorola MPC823 electrical specifications 27 table 3. pcmcia timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max p44 a(6:31), reg valid to pcmcia strobe asserted 28 ? 13 ? 13 ? ns p45 a(6:31), reg valid to ale negation 38 ? 18 ? 18 ? ns p46 clkout to reg valid 10 19 5 13 5 13 ns p47 clkout to reg invalid 11 ?6?6?ns p48 clkout to ce 1, ce 2 asserted 10 19 5 13 5 13 ns p49 clkout to ce 1, ce 2 negated 10 19 5 13 5 13 ns p50 clkout to pcoe , iord , pcwe , iowr assert time ?12?11?11ns p51 clkout to pcoe , iord , pcwe , iowr negate time 312211211ns p52 clkout to ale assert time 10 19 5 13 5 13 ns p53 clkout to ale negate time ? 19 ? 13 ? 13 ns p54 pcwe , iowr negated to d(0:31) invalid 8?3?3?ns p55 wait_b valid to clkout rising edge 8?8?8?ns p56 clkout rising edge to wait_b invalid 2?2?2?ns notes: 1. psst = 1. otherwise, add psst times cycle time. 2. psht = 0. otherwise, add psht times cycle time. 3. these synchronous timings detne when the w ait_b signal is detected in order to freeze (or relieve) the pcmcia current cycle. the w ait_b assertion will be effective only if it is detected two cycles before the psl timer expiration.
28 MPC823 electrical specifications motorola figure 22. pcmcia access cycles timing diagram (external bus read) clkout ts a(0:31) reg ce [1:2] pcoe , iord ale d(0:31) pcoe , p44 p45 p46 p48 p52 p50 p53 b18 p47 p49 p51 p52 b19
motorola MPC823 electrical specifications 29 figure 23. pcmcia access cycles timing diagram (external bus write) clkout ts a[0:31] reg ce [1:2] pcoe , iord ale d[0:31] p44 p45 p46 p50 p53 p52 p48 b8 b9 p54 p52 p51 p49 p47
30 MPC823 electrical specifications motorola figure 24. pcmcia wait signals detection timing diagram figure 25. pcmcia wait signals detection timing diagram clkout wait x p55 p56 clkout wait x p55 p56
motorola MPC823 electrical specifications 31 table 4. pcmcia port timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max p57 clkout to opx valid ? 25 ? 19 ? 19 ns p58 hreset negated to opx drive 30 ? 18 ? 18 ? ns p59 ip_bx valid to clkout rising edge 6?5?5?ns p60 clkout rising edge to ip_bx invalid 2?1?1?ns note: *op2 and op3 only. figure 26. pcmcia output port timing diagram figure 27. pcmcia input port timing diagram clkout output signals hreset op2, op3 p58 p57 input signals clkout p59 p60
32 MPC823 electrical specifications motorola table 5. debug port timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max d61 dsck cycle time 120 ? 60 ? 60 ? ns d62 dsck clock pulse width 50 ? 25 ? 25 ? ns d63 dsck rise and fall times 030303ns d64 dsdi input data setup time 8?8?8?ns d65 dsdi data hold time 5?5?5?ns d66 dsck low to dsdo data valid 0 15 0 15 0 15 ns d67 dsck low to dsdo invalid 020202ns figure 28. debug port clock input timing diagram clkout d61 d61 d63 d63 d62 d62
motorola MPC823 electrical specifications 33 figure 29. debug port timing diagram dsck dsdi dsdo d64 d65 d66 d67
34 MPC823 electrical specifications motorola table 6. reset timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max r68 clkout to hreset high impedance ? 20 ? 20 ? 20 ns r69 clkout to sreset high impedance ? 20 ? 20 ? 20 ns r70 rstconf pulse width 680 ? 425 ? 340 ? ns r71 n/a r72 configuration data to hreset rising edge setup time 650 ? 425 ? 350 ? ns r73 configuration data to rstconf rising edge setup time 650 ? 425 ? 350 ? ns r74 configuration data hold time after rstconf negation 0?0?0?ns r75 configuration data hold time after hreset negation 0?0?0?ns r76 hreset and rstconf asserted to data out drive ? 25 ? 25 ? 25 ns r77 rstconf negated to data out high impedance ? 25 ? 25 ? 25 ns r78 clkout of last rising edge before chip three-states hreset to data out high impedance ?25?25?25 ns r79 dsdi and dsck setup 120 ? 75 ? 60 ? ns r80 dsdi and dsck hold time 0?0?0?ns r81 sreset negated to clkout rising edge for dsdi and dsck sample 320 ? 200 ? 160 ? ns
motorola MPC823 electrical specifications 35 figure 30. reset timing diagram (configuration from data bus) figure 31. reset timing diagrameMPC823 data bus weak drive during configuration hreset rstconf d(0:31) (in) r75 r74 r73 r76 r71 clkout hreset d(0:31) (out) rstconf (weak) r77 r78 r79 r69
36 MPC823 electrical specifications motorola figure 32. reset timing diagramedebug port configuration clkout sreset dsck, dsdi r70 r82 r80 r81 r81 r80
motorola MPC823 electrical specifications 37 table 7. jtag timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max j82 tck cycle time 100 ? 100 ? 100 ? ns j83 tck clock pulse width measured at 1.5v 40 ? 40 ? 40 ? ns j84 tck rise and fall times 0 10 0 10 0 10 ns j85 tms, tdi data setup time 5?5?5?ns j86 tms, tdi data hold time 25 ? 25 ? 25 ? ns j87 tck low to tdo data valid ? 27 ? 27 ? 27 ns j88 tck low to tdo data invalid 0?0?0?ns j89 tck low to tdo high impedance ? 20 ? 20 ? 20 ns j90 trst assert time 100 ? 100 ? 100 ? ns j91 trst setup time to tck low 40 ? 40 ? 40 ? ns j92 tck falling edge to output valid ? 50 ? 50 ? 50 ns j93 tck falling edge to ouput valid out of high impedance ? 50 ? 50 ? 50 ns j94 tck falling edge to output high impedance ? 50 ? 50 ? 50 ns j95 boundary scan input valid to tck rising edge 50 ? 50 ? 50 ? ns j96 tck rising edge to boundary scan input invalid 50 ? 50 ? 50 ? ns figure 33. jtag test clock input timing diagram tck j84 j83 j82 j82 j84 j83
38 MPC823 electrical specifications motorola figure 34. jtagetest access port timing diagram figure 35. jtagetrst timing diagram tck tms, tdi tdo j85 j86 j88 j87 j89 tck trst j91 j90
motorola MPC823 electrical specifications 39 figure 36. boundary scan (jtag) timing diagram tck output signals output signals output signals j92 j94 j93 j96 j95
40 MPC823 electrical specifications motorola communication electrical characteristics table 8. parallel input/output port timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 29 data-in setup time to clock high 20 ? 15 ? 15 ? ns 30 data-in hold time from clock high 10 ? 7.5 ? 7.5 ? ns 31 clock high to data-out valid (cpu writes data, control, or direction) ?25?25?25ns figure 37. parallel input/output data-in/data-out timing diagram clkout data in data out 29 31 30
motorola MPC823 electrical specifications 41 table 9. idma timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 40 dreq setup time to clock high 12 ?7?7? nsec 41 dreq hold time from clock high 5?3?3? nsec 42 sdack assertion delay from clock high ? 20 ? 12 ? 12 nsec 43 sdack negation delay from clock low ? 20 ? 12 ? 12 nsec 44 sdack negation delay from ta low ? 25 ? 20 ? 20 nsec 45 sdack negation delay from clock high ? 20 ? 15 ? 15 nsec 46 ta assertion to falling edge of the clock setup time 12?7?7? nsec note: applies to external ta . figure 38. idma external requests timing diagram clkout dreq (input) (output) 41 40
42 MPC823 electrical specifications motorola figure 39. sdack timing diagrameperipheral write, ta sampled low at the falling edge of the clock sdack clkout (output) ts (output) rd / wr (output) data ta (output) 42 46 43
motorola MPC823 electrical specifications 43 figure 40. sdack timing diagrameperipheral write, ta sampled high at the falling edge of the clock sdack clkout (output) ts (output) rd / wr (output) data ta (output) 42 44
44 MPC823 electrical specifications motorola figure 41. sdack timing diagrameperipheral read sdack clkout (output) ts (output) rd / wr (output) data ta (output) 42 45
motorola MPC823 electrical specifications 45 table 10. baud rate generator timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 50 brgo rise and fall times ? 10 ? 10 ? 10 ns 51 brgo duty cycle 40 60 40 60 40 60 % 52 brgo cycle 40 ? 40 ? 40 ? ns figure 42. baud rate generator timing diagram brgox 50 50 51 51 52
46 MPC823 electrical specifications motorola table 11. general-purpose timers timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 61 tin/tgate rise and fall times 12 10 7 10 7 10 ns 62 tin/tgate low time 513131clk 63 tin/tgate high time ? 20 ? 12 ? 12 clk 64 tin/tgate cycle time ? 20 ? 12 ? 12 clk 65 clko low to tout valid ? 25 ? 20 ? 20 ns figure 43. general-purpose timers timing diagram clkout tin / tgate (input) tout (output) 61 60 63 62 64 61 65
motorola MPC823 electrical specifications 47 table 12. serial interface timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 70 l1rclk and l1tclk frequency (dsc=0) 1,3 ?10?10?10 mhz 71 l1rclk and l1tclk width low (dsc=0) 3 p+10 ? p+10 ? p+10 ? ns 71a l1rclk and l1tclk width high (dsc=0) 2 p+10 ? p+10 ? p+10 ? ns 72 l1txd, l1st(1e8), l1rq, l1clko rise and fall times ?15?15?15 ns 73 l1rsync, l1tsync valid to l1clk edge (sync setup time) 20?20?20? ns 74 l1clk edge to l1rsync and l1tsync invalid (sync hold time) 35?35?35? ns 75 l1rsync and l1tsync rise and fall times ? 15 ? 15 ? 15 ns 76 l1rxd valid to l1clk edge (l1rxd setup time) 42 ? 42 ? 42 ? ns 77 l1clk edge to l1rxd invalid (l1rxd hold time) 35 ? 35 ? 35 ? ns 78 l1clk edge to l1st(1e8) valid 10 45 10 45 10 45 ns 78a l1sync valid to l1st(1e8) valid 4 10 45 10 45 10 45 ns 79 l1clk edge to l1st(1e8) invalid 10 45 10 45 10 45 ns 80 l1clk edge to l1txd valid 10 65 10 65 10 65 ns 80a l1tsync valid to l1txd valid 4 10 65 10 65 10 65 ns 81 l1clk edge to l1txd high impedance 0 42 0 42 0 42 ns 82 l1rclk and l1tclk frequency (dsc=1) ? 12.5 ? 16 ? 16 mhz 83 l1rclk and l1tclk width low (dsc=1) p+10 ? p+10 ? p+10 ? ns 83a l1rclk and l1tclk width high (dsc=1) 2 p+10 ? p+10 ? p+10 ? ns 84 l1clk edge to l1clko valid (dsc=1) ? 30 ? 30 ? 30 ns 85 l1rq valid before falling edge of l1tsync 3 1?1?1? l1tclk 86 l1gr setup time 3 42?42?42? ns 87 l1gr hold time 3 42?42?42? ns 88 l1clk edge to l1sync valid (fsd = 00, cnt = 0000, byt = 0, dsc=0) ?0?0?0 ns notes: 1. the ratio syncclk/l1rclk must be greater than 2.5/1. 2. where p=1/clko1. for a 25mhz clko1 rate, p=40ns. 3. these electrical specitcations are only valid for idl mode. 4. the strobes and txd2 on the trst bit of the frame becomes valid after l1clk edge or l1sync, whichever is later.
48 MPC823 electrical specifications motorola figure 44. serial interface receive timing diagram with normal clocking (dsc =0) bit0 rfcd=1 l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1rxd (input) l1st(1-4) (output) 71 70 72 75 73 74 77 76 78 79
motorola MPC823 electrical specifications 49 figure 45. serial interface transmit timing diagram tfcd=0 l1tclk (fe=0, ce=0) (input) l1tclk (fe=1, ce=1) (input) l1tsync (input) l1txd (output) l1st(1-4) (output) bit0 71 70 72 73 75 74 80a 80 78a 78 79 81
50 MPC823 electrical specifications motorola table 13. serial communication controller in nmsi external timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 100 rclk1 and tclk1 width high 1 clkout f ? clkout f ? clkout f ? mhz 101 rclk1 and tclk1 width low clkout +5ns ? clkout +5ns ? clkout +5ns ?ns 102 rclk1 and tclk1 rise and fall times ? 15 ? 15 ? 15 ns 103 txd2 active delay (from tclk1 falling edge) 050050050ns 104 rts1 active/inactive delay (from tclk1 falling edge) 050050050ns 105 cts1 setup time to tclk1 rising edge 5?5?5?ns 106 rxd2 setup time to rclk1 rising edge 5?5?5?ns 107 rxd2 hold time from rclk1 rising edge 2 5?5?5?ns 108 cd1 setup time to rclk1 rising edge 5?5?5?ns notes: 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 2.25/1. 2. applies to cd and cts hold time when they are used as external sync signals.
motorola MPC823 electrical specifications 51 table 14. serial communication controller in nmsi internal timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 100 rclk1 and tclk1 frequency 1 0 8.3 0 13 0 16 mhz 102 rclk1 and tclk1 rise and all times ??????ns 103 txd2 active delay (from tclk1 falling edge) 030030030ns 104 rts1 active/inactive delay (from tclk1 falling edge) 030030030ns 105 cts1 setup time to tclk1 rising edge 40 ? 40 ? 40 ? ns 106 rxd2 setup time to rclk1 rising edge 40 ? 40 ? 40 ? ns 107 rxd2 hold time from rclk1 rising edge 2 0?0?0?ns 108 cd1 setup time to rclk1 rising edge 40 ? 40 ? 40 ? ns notes: 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 3/1. 2. applies to cd and cts hold time when they are used as external sync signals. figure 46. scc nmsi receive timing diagram rclk1 rxd2 (input) cd1 (input) cd1 (sync input) 102 102 101 100 107 106 108 107
52 MPC823 electrical specifications motorola figure 47. scc nmsi transmit timing diagram tclk1 txd2 (output) rts1 (output) cts1 (input) cts1 (sync input) 102 102 101 100 103 104 105 104 107
motorola MPC823 electrical specifications 53 figure 48. hdlc bus timing diagram tclk1 txd2 (output) rts1 (output) cts1 (echo input) 102 101 100 103 104 105 107 104 102
54 MPC823 electrical specifications motorola table 15. ethernet timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 120 clsn (cts2) width high 40 ? 40 ? 40 ? ns 121 rclk1 rise and fall times ? 15 ? 15 ? 15 ns 122 rclk1 width low 40 ? 40 ? 40 ? ns 123 rclk1 clock period 1 80 120 80 120 80 120 ns 124 rxd2 setup time 20 ? 20 ? 20 ? ns 125 rxd2 hold time 5?5?5?ns 126 rena (cd2) active delay (from rclk1 rising edge of the last data bit) 10?10?10?ns 127 rena (cd2) width low 100 ? 100 ? 100 ? ns 128 tclk1 rise and fall times ? 15 ? 15 ? 15 ns 129 tclk1 width low 40 ? 40 ? 40 ? ns 130 tclk1 clock period 1 99 101 99 101 99 101 ns 131 txd2 active delay (from tclk1 rising edge) 10 50 10 50 10 50 ns 132 txd2 inactive delay (from tclk1 rising edge) 10 50 10 50 10 50 ns 133 tena (rts2) active delay (from tclk1 rising edge) 10 50 10 50 10 50 ns 134 tena (rts2) inactive delay (from tclk1 rising edge) 10 50 10 50 10 50 ns 135 n/a 136 n/a 137 n/a 138 clkx low to sdack asserted 2 ?20?20?20ns 139 clkx low to sdack negated 3 ?20?20?20ns notes: 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 2/1. 2. sdack is asserted when the sdma writes the incoming frame da into memory.
motorola MPC823 electrical specifications 55 figure 49. ethernet collision timing diagram figure 50. ethernet receive timing diagram clsn ( cts1 ) (input) 120 rclk1 rxd2 rena (cd1) (input) (input) last bit 121 121 123 127 126 125 124
56 MPC823 electrical specifications motorola figure 51. ethernet transmit timing diagram tclk1 txd2 rena (cd1) (input) (output) tena (rts1) (input) (note 2) notes: 1. transmit clock invert (tci) bit in the gsmr is set. 2. if rena is deasserted before tena, or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of frame transmission. 128 128 132 121 131 133 129 134
motorola MPC823 electrical specifications 57 table 16. serial peripheral interface master timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 160 master cycle time 4 1,024 4 1,024 4 1,024 tcyc 161 master clock (sck) high or low time 2 512 2 512 2 512 tcyc 162 master data setup time (inputs) 50 ? 50 ? 50 ? ns 163 master data hold time (inputs) 0?0?0?ns 164 master data valid (after sck edge) ? 20 ? 20 ? 20 ns 165 master data hold time (outputs) 0?0?0?ns 166 rise time output ? 15 ? 15 ? 15 ns 167 fall time output ? 15 ? 15 ? 15 ns note: the ratio syncclk/smclk must be greater than or equal to 2/1. figure 52. spi master (cp=0) timing diagram spiclk ci=0 (output) spiclk ci=1 (output) spimiso (input) spimosi (output) msb in data lsb in msb in msb out data lsb out msb out 161 161 160 166 167 166 167 163 162 165 164 166 167
58 MPC823 electrical specifications motorola figure 53. spi master (cp=1) timing diagram spiclk ci=0 (output) spiclk ci=1 (output) spimiso (input) spimosi (output) msb in data lsb in msb in msb out data lsb out msb out 161 161 167 160 166 167 166 163 162 165 164 166 167
motorola MPC823 electrical specifications 59 table 17. serial peripheral interface slave timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 170 slave cycle time 2?2?2? tcyc 171 slave enable lead time 15 ? 15 ? 15 ? ns 172 slave enable lag time 15 ? 15 ? 15 ? ns 173 slave clock (spiclk) high or low time 1?1?1? tcyc 174 slave sequential transfer delay (does not require deselect) 1?1?1? tcyc 175 slave data setup time (inputs) 20 ? 20 ? 20 ? ns 176 slave data hold time (inputs) 20 ? 20 ? 20 ? ns 177 slave access time ? 50 ? 50 ? 50 ns 178 slave spi miso disable time ? 50 ? 50 ? 50 ns 179 slave data valid (after spiclk edge) ? 50 ? 50 ? 50 ns 180 slave data hold time (outputs) 0?0?0?ns 181 rise time (input) ? 15 ? 15 ? 15 ns 182 fall time (input) ? 15 ? 15 ? 15 ns
60 MPC823 electrical specifications motorola figure 54. spi slave (cp=0) timing diagram spiclk ci=0 (input) spiclk ci=1 (input) spimiso (output) spimosi (input) msb out data lsb out msb out msb in data lsb in msb in spisel (input) undef 173 173 182 170 181 174 172 171 178 182 181 179 181 182 176 175 177 180
motorola MPC823 electrical specifications 61 figure 55. spi slave (cp=1) timing diagram spiclk ci=0 (input) spiclk ci=1 (input) spimiso (output) spimosi (input) spisel (input) undef data lsb out msb out msb in data lsb in msb in msb out 171 173 173 170 182 172 174 178 180 182 181 181 179 176 175 182 181 177
62 MPC823 electrical specifications motorola table 18. i 2 c timing?scl < 100 khz num characteristic 25mhz 40mhz 50mhz unit min max min max min max 200 scl clock frequency (slave) 0 100 0 100 0 100 khz 200 scl clock frequency (master) 1.5 100 1.5 100 1.5 100 khz 202 bus free time between transmissions 4.7 ? 4.7 ? 4.7 ? m s 203 low period of scl 4.7 ? 4.7 ? 4.7 ? m s 204 high period of scl 4.0 ? 4.0 ? 4.0 ? m s 205 start condition setup time 4.7 ? 4.7 ? 4.7 ? m s 206 start condition hold time 4.0 ? 4.0 ? 4.0 ? m s 207 data hold time 0?0?0? m s 208 data setup time 250 ? 250 ? 250 ? ns 209 sdl/scl rise time ?1?1?1 m s 210 sdl/scl fall time ? 300 ? 300 ? 300 ns 211 stop condition setup time 4.7 ? 4.7 ? 4.7 ? m s note: scl frequency is given by scl = brgclk_frequency/((brg register + 3) * pre_scaler * 2 ). the ratio syncclk/(brgclk/pre_scaler) must be greater than or equal to 4/1. table 19. i 2 c timing?scl > 100 khz num characteristic minimum maximum unit 200 scl clock frequency (slave) 0 brgclk/48 hz 200 scl clock frequency (master) brgclk/16512 brgclk/48 hz 202 bus free time between transmissions 1/(2.2 * fscl) ? sec 203 low period of scl 1/(2.2 * fscl) ? sec 204 high period of scl 1/(2.2 * fscl) ? sec 205 start condition setup time 1/(2.2 * fscl) ? sec 206 start condition hold time 1/(2.2 * fscl) ? sec 207 data hold time 0 ? sec 208 data setup time 1/(40 * fscl) ? sec 209 sdl/scl rise time ? 1/(10 * fscl) sec 210 sdl/scl fall time ? 1/(33 * fscl) sec 211 stop condition setup time 1/(2.2 * fscl) ? sec
motorola MPC823 electrical specifications 63 figure 56. i 2 c bus timing diagram sda scl 202 205 203 207 204 208 210 209 206 211
64 MPC823 electrical specifications motorola table 20. serial management controller timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 150 clk1 clock period 100 ? 100 ? 100 ? ns 151 clk1 width low 50 ? 50 ? 50 ? ns 151a clk1 width high 50 ? 50 ? 50 ? ns 152 clk1 rise and fall times ? 15 ? 15 ? 15 ns 153 smtxdx active delay (from clk1 falling edge) 10 50 10 50 10 50 ns 154 smrxdx/sync1 setup time 20 ? 20 ? 20 ? ns 155 smrxdx/sync1 hold time 5?5?5?ns note: the ratio syncclk/smclk must be greater than or equal to 2/1. figure 57. smc transparent timing diagram 150 note: * this delay is equal to an integer number of character length clocks. smclk smtxdx (output) sync1 smrxdx (input) * 152 152 151 161a 153 155 154 154 155
motorola MPC823 electrical specifications 65 tcyc is the cycle time of the lcd clock (shift clock). tdelay is a circuit delay that is specified in the ac electrical specifications. 1e16 lines is a time period that can vary between one scan line and 16, depending on how the lcd controller is programmed in the vpw field of the lcvcr. 0e1,023 lines is a time period that can vary between 0 and 1,023 scan lines in the wbf field of the lcvcr. table 21. lcd controller timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 220 shift clock cycle time 40 ? 40 ? 40 ? nsec 221 shift clock high time 20 ? 20 ? 20 ? nsec 223 clock/hsync/vsync/oe rise and fall times ? 10 ? 10 ? 10 nsec 224 data valid delay from shift clock high ? 15 ? 15 ? 15 nsec 225 vsync to hsync setup time 1 5?5?5?t 226 vsync hold time 1?1?1?t 227 hsync pulse width 4?4?4?t 228 time from clock falling edge to hsync rising edge 4.5 ? 4.5 ? 4.5 ? t 229 time from hsync falling edge to clock rising edge 2 4?4?4?t 230 ac active delay ? 25 ? 25 ? 25 nsec 231 vsync pulse width (tft) 1 16 1 16 1 16 line 232 hsync to oe delay 3 4?4?4?t 233 oe to hsync delay 4?4?4?t 234 vsync to oe delay (tft) 0 1,023 0 1,023 0 1,023 t 235 vsync/hsync/oe active delay (tft) ? 15 ? 15 ? 15 nsec 236 wait between frames 4 wbf ? wbf ? wbf ? line notes: 1. t = shift clock cycle (220). 2. this number is given for wbl(wait between lines) 2. for wbl=n {n > 2} the timing will be (n+2)t. 3. this number is given for wbl(wait between lines) 2. for wbl=n {n > 2} the timing will be (n+2)t. 4. wait between frames (wbf) is a programmable parameter.
66 MPC823 electrical specifications motorola figure 58. passive panel timing diagram shift clock data shift clock hsync vsync lcd_ac vsync hsync shift clock nth line first line second line 224 223 223 220 221 228 227 229 226 225 230 236
motorola MPC823 electrical specifications 67 figure 59. tft panel timing diagram shift data oe vsync hsync oe first line nth line hsync vsync oe 227 235 224 233 235 234 231 232 225 235
68 MPC823 electrical specifications motorola table 22. video controller timing num characteristic 25mhz 40mhz 50mhz unit min max min max min max 240 clock cycle time 32 ? 32 ? 32 ? nsec 241 clock high time 13 ? 13 ? 13 ? nsec 242 clk/hsync /vsync /blank /field rise and fall times ? 10 ? 10 ? 10 nsec 243 clock high to data valid 10 25 10 25 10 25 nsec figure 60. video controller timing clk data hsync vsync field blank 243 242 242 240 241
motorola MPC823 electrical specifications 69
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